1. Field of the Invention
The present invention relates to a semiconductor memory device, more particularly to a data path control circuit designed to curtail the charge and discharge current of the data path.
2. Related Art
In recent years, with the acceleration in speed of CPU, demands for high speed operation of semiconductor memory device have enhanced. To meet such requirements there have been proposed the synchronous type semiconductor memory devices which work in synchronization with the external clocks exceeding 100 MHz. As the known literature on such kinds of semiconductor memory devices, references are made for example to Japanese Patent Application Laid-Open No. 61-148692 (Title of the Invention: "Memory Device"), Japanese Patent Application Laid-Open No. 6-76566 (Title of the Invention: "Semiconductor Memory Device"), Japanese Patent Application Laid-Open No. 7-45068 (Title of the Invention: "Synchronous Type Semiconductor Memory Device"), and the like.
An example of the constitutions of these conventional synchronous type semiconductor devices is shown in FIG. 7. Referring to FIG. 7, an input buffer 1 inputs an address signal ADD, an input buffer 2 inputs an external clock CLK and an input buffer 3 connected to a terminal DQ inputs written data. An internal synchronous signal generating circuit 5 inputs an output of the input buffer 2 and outputs an internal synchronous signal ICLK1 and ICLK2. A burst counter 12 inputs an output of the input buffer 1 and an internal synchronous signal ICLK1 and outputs an internal column address signal IADD. A D-type flip-flop (D-F/F) circuit 6 inputs an output of the input buffer 3 and drives a write bus WBUS1 in synchronization with the internal synchronous signal ICLK1. A D-F/F circuit 7 inputs a write bus WBUS1 and drives a write bus WBUS2 in synchronization with the internal synchronous signal ICLK2. A column decoder 8 inputs an internal column address signal IADD and outputs a column switch YSW. Sense amplifiers 9 input a column switch YSW and a write bus WBUS2. A memory cell array 10 is connected to the sense amplifiers 9 through a bit line.
An example of the operations of the conventional synchronous type semiconductor memory device is shown as a timing waveform diagram in FIG. 8. The internal synchronous signal ICLK1 is a pulse readily formed from the rising edge (transition from Low level to High level) of the external clock CLK, and the internal synchronous signal ICLK2 is a pulse formed after the predetermined delay from the internal synchronous signal ICLK1.
When Y=0 is given to an external address signal ADD at the rising edge of the external clock CLK in the C1 cycle which becomes the starting point of the writing operation, there are produced the internal column address IADD of Y=0, Y=1, Y=2, and Y=3, respectively, in the cycles of C1, C2, C3 and C4, in synchronization with the internal synchronous signal ICLK1. This is because this synchronous type semiconductor memory device has an operating function at the burst length 4, wherein, by the external address input of one time, the internal column address signals IADD of the number of burst length are formed in the burst counter 12.
The sequential order of this internal column address is determined by the external address signal in C1 cycle and the type of burst.
TABLE 1 ______________________________________ Sequential type internal column address STARTING ADDRESS INTERNAL ADDRESS A1 A0 SEQUENCE (DECIMAL) ______________________________________ 0 0 0,1,2,3 0 1,2,3,0 1 2,3,0,1 1 3,0,1,2 ______________________________________
Table 1 shows a case where the type of the burst is a sequential type, in which, according to the logic level of the lower 2 bits (A1, A0) of the external address signal ADD in C1 cycle, the lower 2 bits vary in the order shown in Table 1. In case the burst length is "4", the portions other than the lower 2 bits are fixed.
TABLE 2 ______________________________________ Interleave type internal column address STARTING ADDRESS INTERNAL ADDRESS A1 A0 SEQUENCE (DECIMAL) ______________________________________ 0 0 0,1,2,3 0 1,0,3,2 1 2,3,0,1 1 3,2,1,0 ______________________________________
Table 2 shows the case where the burst type is an inter-leave type, where the lower 2 bits only vary in the same manner.
As reviewed above, the art which has a burst counter 12 and automatically forms addresses in order internally has come to be generalized along with the tendency for the CPU to become high speed, and there are more frequently available the synchronous type semiconductor memory devices wherein the two types of the sequential type in which the lower 2 bits are subjected to increment in order as the address sequence and the inter-leave type in which an exclusive logical sum of present address and starting address is selected as the next address, may be selected by the user.
In FIG. 8, IY0 shows the lowermost bit of the internal column address, and IY1 shows the second bit from the lower part of the internal column address. IY0 varies in synchronization with the internal synchronous signal ICLK1 as Low, High, Low, High, and IY1 likewise varies as Low, Low, High, High. The column switch YSW varies according to the internal column address IADD.
Further, when the write-in data to the terminal DQ in each cycle of C1, C2, C3, C4 are sequentially set to be Low, High, Low, High, the level of the write bus WBUS1 varies as Low, High, Low, High in synchronization with the internal synchronous signal ICLK1, and the level of the write bus WBUS2 varies as Low, High, Low, High in synchronization with the internal synchronous signal ICLK2.
By adjusting the formation of the internal synchronous signal ICLK2 to be in tune with the selection of the column switch YSW, the write-in data on the write bus WBUS2 can be written in the sense amplifier selected by the column switch YSW in the sense amplifiers 9. Thereafter, the write-in data are written in the memory cell in the memory cell array 10 through the bit line.
In the write bus WBUS1, WBUS2 there exist the parasitic capacities C1, C2, respectively (ref. FIG. 1), and when the write-in data on each cycle vary as in the example of FIG. 8, the charge for the capacity of (C1+C2) is to be charged or discharged for each cycle.
However, as the conventional semiconductor memory device as described above is so constituted that, according to the variation of the write-in data in the terminal DQ, the levels of the write bus WBUS1, WBUS2 also vary accordingly, there is a problem that, in case of the change of the write-in data on each cycle, the parasitic capacities C1 and C2 are charged or discharged on each cycle.
In consequence of the increase in the chip size resulting from the enlargement in capacity of the semiconductor memory device in recent years, there is a tendency for the wiring length of the write bus to become longer, with increase in the parasitic capacity thereof.
Furthermore, there is also a tendency for a plurality of the terminals DQ for inputting the write-in data to be provided so as to write a large number of data in parallel. Accompanied with this, a plurality of write buses WBUS 1, 2 are provided. Accordingly, the subject of increase in current consumption due to the charge and discharge of write bus can no longer be neglected.